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Omni
General Description
ision
TM
Advanced Information Preliminary Datasheet
OV7640 Color CMOS VGA (640 x 480) CAMERACHIPTM OV7141 B&W CMOS VGA (640 x 480) CAMERACHIPTM Applications
* * * Cellular and Picture Phones Toys PC Multimedia
The OV7640 (color) and OV7141 (black and white) CAMERACHIPSTM are low voltage CMOS image sensors that provide the full functionality of a single-chip VGA (640 x 480) camera and image processor in a small footprint package. The OV7640/OV7141 provides full-frame, sub-sampled or windowed 8-bit images in a wide range of formats, controlled through OmniVision's Serial Camera Control Bus (SCCB) interface. This product family has an image array capable of operating at up to 30 frames per second (fps) with complete user control over image quality, formatting and output data transfer. All required image processing functions, including exposure control, gamma, white balance, color saturation, hue control and more, are also programmable through the SCCB interface. In addition, OmniVision CAMERACHIPs use proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination such as fixed pattern noise, smearing, blooming, etc. to produce a clean, fully stable color image.
Key Specifications
Power Supply Power Requirements Array Size Core Analog I/O Active 640 x 480 (VGA) 2.5VDC + 10% 2.5VDC + 4% 2.25V to 3.3V 40 mW (30 fps, including I/O power) 30 W -10C to 70C 0C to 50C * YUV/YCbCr 4:2:2 * RGB 4:2:2 * Raw RGB Data 1/4" 30 fps 60 fps 3.0 V/Lux-sec 1.12 V/Lux-sec 46 dB 62 dB Progressive/Interlaced 523 x tROW 0.45 5.6 m x 5.6 m 30 mV/s 60 Ke < 0.03% of VPEAK-TO-PEAK 3.6 mm x 2.7 mm 11.43 mm x 11.43 mm
Standby Temperature Operation Range Stable Image Output Formats (8-bit)
Maximum Image Transfer Rate
Features
* * * * High sensitivity for low-light operation 2.5V operating voltage for embedded portable applications Standard Serial Camera Control Bus (SCCB) interface VGA, QVGA (sub-sampled) and Windowed outputs with Raw RGB, RGB (GRB 4:2:2), YUV (4:2:2) and YCbCr (4:2:2) formats Automatic image control functions including: Automatic Exposure Control (AEC), Automatic Gain Control (AGC), Automatic White Balance (AWB), Automatic Brightness Control (ABC), Automatic Band Filter (ABF) for 60Hz noise and Automatic Black-Level Calibration (ABLC) Image quality controls including color saturation, hue, gamma, sharpness (edge enhancement), anti-blooming and zero smearing
Lens Size VGA QVGA B&W Sensitivity Color S/N Ratio Dynamic Range Scan Mode Maximum Exposure Interval Gamma Correction Pixel Size Dark Current Well Capacity Fixed Pattern Noise Image Area Package Dimensions
*
Figure 1 OV7640/OV7141 Pin Diagram
VDD_ A VSS_ A SIO_D 27 NC SIO_C 26 NC NC 28
4
3
2
1
PWDN NC VREF VDD_C VSYNC
5 6 7 8 9 10 11
25 24 23
Y0 Y1 Y2 Y3 Y4 Y5 Y6
*
Ordering Information
Product OV7640 (Color) OV7141 (B&W) Package PLCC-28 PLCC-28
OV7640/OV7141
22 21 20 19
HREF PCLK
12 VDD_IO
13 CLK
14 NC
15 RESET
16 NC
17 VSS_D
18 Y7
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OV7640/OV7141
CMOS VGA (640 x 480) CAMERACHIPTM
Omni
ision
Functional Description
Figure 2 shows the functional block diagram of the OV7640/OV7141 image sensor. The OV7640/OV7141 includes: * Image Sensor Array (640 x 480 resolution) Timing Generator * Analog Processing Block * A/D Converters * * Output Formatter * Digital Video Port * SCCB Interface
Figure 2 OV7640/OV7141 Functional Block Diagram
Analog Processing
R
G
B
MUX
A/D
Output Formatter Data Formatting
Saturation Hue Brightness
Gain WB Gamma Y Cb MUX Cr A/D
Windowing
Image Array (640 x 480)
Row Select
Control Registers (To all circuits)
Digital Video Port
Y[7:0]
Column Sense Amps RESET PWDN Timing Generator SCCB Interface
VREF 1.0 f
CLK HREF PCLK VSYNC SIO_C SIO_D
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ision
Functional Description
Image Sensor Array
The OV7640/OV7141 CAMERACHIPS has an active image array size of 640 columns x 480 rows (307,200 pixels). However, the full array contains 652 columns and 486 rows, with the extra 6 rows used for black-level calibration ("Optical Black") and color interpolation information. Figure 3 shows a cross-section of the image sensor array.
A/D Converters
After the Analog Processing Block, the color channel data signal is fed to two 8-bit Analog-to-Digital (A/D) converters via the multiplexers, one for the Y/G channel and one shared by the CrCb/BR channels. These A/D converters operate at speeds up to 12MHz, and are fully synchronous to the pixel rate (actual conversion rate is related to the frame rate). In addition to the A/D conversion, this block also has the following functions: * Digital Black-Level Calibration (BLC) * Optional U/V channel delay * Additional A/D range controls In general, the combination of the A/D Range Multiplier and A/D Range Control sets the A/D range and maximum value to allow the user to adjust the final image brightness as a function of the individual application.
Figure 3 Image Sensor Array
Microlens
Color Filter
Photo Diode
Timing Generator
In general, the timing generator controls these functions: * Array control and frame generation (VGA and QVGA outputs) * Internal timing signal generation and distribution * Frame rate timing * Automatic Exposure Control (AEC) * External timing outputs (VSYNC, HREF and PCLK)
Output Formatter
This block controls all output and data formatting required prior to sending the image out.
Digital Video Port
These two bits increase IOL / IOH drive current and can be adjusted as a function of the customer's loading:
Analog Processing Block
This block performs all analog image functions including: * Automatic Gain Control (AGC) * Automatic White Balance (AWB) * Image quality controls including: - Color saturation - Hue - Gamma - Sharpness (edge enhancement) - Anti-blooming - Zero smearing
SCCB Interface
The Serial Camera Control Bus (SCCB) interface controls the CAMERACHIP operation. Refer to OmniVision Technologies Serial Camera Control Bus (SCCB) Specification for detailed usage of the serial control port.
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OV7640/OV7141 Pin Description
Table 1
Pin Number 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
CMOS VGA (640 x 480) CAMERACHIPTM
Omni
ision
Pin Description
Name VSS_A VDD_A NC NC PWDN NC VREF VDD_C VSYNC HREF PCLK VDD_IO CLK NC RESET NC VSS_D Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 SIO_C SIO_D NC Pin Type Ground VDD -- -- Input -- VREF VDD Output Output Output VDD Input -- Input -- Ground Output Output Output Output Output Output Output Output Input I/O -- Analog ground Analog VDD No connection No connection Sets device to power down standby mode No connection Internal voltage reference (2.3V). Connect to ground through 1F capacitor Core VDD Vertical sync output HREF output Pixel clock output I/O VDD External clock No connection Clears all registers and resets them to their default values. No connection Digital ground Digital video output bit[7] Digital video output bit[6] Digital video output bit[5] Digital video output bit[4] Digital video output bit[3] Digital video output bit[2] Digital video output bit[1] Digital video output bit[0] SCCB serial interface clock SCCB serial interface data I/O No connection Function/Description
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ision
Electrical Characteristics
Electrical Characteristics
Table 2 Absolute Maximum Ratings
-40C to +125C VDD-A Supply Voltages (with respect to Ground) VDD-C VDD-IO All Input/Output Voltages (with respect to Ground) Lead Temperature, Surface-mount process ESD Rating, Human Body model NOTE: 3V 3V 4V -0.3V to VDD_IO+1V +230C 2000V
Ambient Storage Temperature
Exceeding the Absolute Maximum ratings shown above invalidates all AC and DC electrical specifications and may result in permanent device damage.
Table 3
Symbol VDD-A VDD-C VDD-IO IDDA IDDS-SCCB IDDS-PWDN VIH VIL VOH VOL IOH IOL IL
a. b. c.
DC Characteristics (0C < TA < 70C)
Parameter DC supply voltage - Analog DC supply voltage - Core DC supply voltage - I/O Active (Operating) Current Standby Current Standby Current Input voltage HIGH Input voltage LOW Output voltage HIGH Output voltage LOW Output current HIGH Output current LOW Input/Output Leakage GND to VDD-IO See Note c 8 15 1 CMOS (IOH / IOL) 0.9 x VDD-IO 0.1 x VDD-IO Condition -- -- -- See Note a See Note b CMOS 0.7 x VDD-IO 0.3 x VDD-IO Min 2.40 2.25 2.25 Typ 2.5 2.5 -- 15 1 10 Max 2.60 2.75 3.3 Unit V V V mA mA A V V V V mA mA A
VDD-A = VDD-C = 2.5V, VDD-IO = 3.0V IDDA = {IDD-IO+ IDD-C + IDD-A}, fCLK = 24MHz at 30 fps, no I/O loading VDD-A = VDD-C = 2.5V, VDD-IO = 3.0V IDDS:SCCB refers to a SCCB-initiated Standby, while IDDS:PWDN refers to a PWDN pin-initiated Standby Standard Output Loading = 25pF, 1.2K to 3V
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OV7640/OV7141
CMOS VGA (640 x 480) CAMERACHIPTM
Omni
ision
Table 4
Symbol
Functional and AC Characteristics (0C < TA < 70C)
Parameter A/D A/D AGC Differential Non-Linearity Integral Non-Linearity Range Red/Blue Adjustment Range Min Typ + 1/2 +1 21 12 10 100 45 24 42 50 27 37 55 1 300 Max Unit LSB LSB dB dB MHz ns % ms ms
Functional Characteristics
Inputs (PWDN, CLK, RESET) fCLK tCLK tCLK:DC tS:RESET tS:REG fSIO_C tLOW tHIGH tAA tBUF tHD:STA tSU:STA tHD:DAT tSU:DAT tSU:STO tR, tF tDH tPDV tSU tHD tPHH tPHL Input Clock Frequency Input Clock Period Clock Duty Cycle Setting time after software/hardware reset Settling time for register change (10 frames required)
SCCB (SIO_C and SIO_D - see Figure 4) Clock Frequency Clock Low Period Clock High Period SIO_C low to Data Out valid Bus free time before new START START condition Hold time START condition Setup time Data-in Hold time Data-in Setup time STOP condition Setup time SCCB Rise/Fall times Data-out Hold time 50 1.3 600 100 1.3 600 600 0 100 600 300 900 400 KHz s ns ns s ns ns s ns ns ns ns
Outputs (VSYNC, HREF, PCLK, and Y[7:0] - see Figure 5, Figure 6, and Figure 7) PCLK[] to Data-out Valid Y[7:0] Setup time Y[7:0] Hold time PCLK[] to HREF[] PCLK[] to HREF[] * VDD: AC Conditions: VDD-A = VDD-C = 2.5V, VDD-IO = 3.3V 5ns, Maximum SCCB: 300ns, Maximum * * * Input Capacitance: 10pf Output Loading: 25pF, 1.2K to 3V 24MHz fCLK: Version 1.4, March 6, 2003 15 8 0 0 5 5 5 ns ns ns ns ns
* Rise/Fall Times: I/O:
6
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ision
Timing Specifications
Timing Specifications
Figure 4 SCCB Timing Diagram
tF tLOW SIO_C tSU:STA SIO_D IN tAA t DH t HD:STA t HD:DAT t SU:DAT tSU:STO t HIGH tR
t BUF
SIO_D OUT
Figure 5 Row Output Timing Diagram
tPCLK PCLK
t PHL HREF tSU t HD Y[7:0] Last Byte First Byte tPDV Last Byte (Row Data)
tPHL
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OV7640/OV7141
CMOS VGA (640 x 480) CAMERACHIPTM
Omni
ision
Figure 6 VGA Frame Timing Diagram
525 t ROW VSYNC 3 t ROW 11 t ROW 764 t PCLK HREF 640 t PCLK Y[7:0] (Invalid Data) Row 0 Row 1 Row 2 Last Row 124 t PCLK (Invalid Data) 31 t ROW
Figure 7 QVGA Frame Timing Diagram
262.5 t ROW VSYNC 3 t ROW 9 t ROW 382 t PCLK HREF 320 t PCLK Y[7:0] (Invalid Data) Row 0 Row 1 Row 2 Last Row 62 t PCLK (Invalid Data) 10.5 t ROW
Note: As the RGB, YUV and YCbCr formats use the Bayer pattern for interpolation, the first row transferred out on the Y[7:0] bus will be invalid, as there is no row above Row #1 to provide the 'pair data' required. Because of this, the OV7640 does not enable the HREF signal during the first row read (shown above in the 'invalid data' zone).
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ision
Timing Specifications
Figure 8 RGB 565 Output Timing Diagram
tPCLK PCLK
t PHL HREF tSU t HD Y[7:0] Last Byte First Byte tPDV Last Byte (Row Data)
tPHL
First Byte Y[7] Y[6] Y[5] Y[4] Y[3] Y[2] Y[1] Y[0] R0 G5 G3 R4
Second Byte G2 G0 B4 Y[7] Y[6] Y[5] Y[4] Y[3] Y[2] Y[1] B0 Y[0]
Figure 9 RGB 555 Output Timing Diagram
tPCLK PCLK
t PHL HREF tSU t HD Y[7:0] Last Byte First Byte tPDV Last Byte (Row Data)
tPHL
First Byte Y[7] Y[6] Y[5] Y[4] Y[3] Y[2] Y[1] Y[0] R0 G4 G3 X R4
Second Byte G2 G0 B4 Y[7] Y[6] Y[5] Y[4] Y[3] Y[2] Y[1] B0 Y[0]
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OV7640/OV7141 Register Set
CMOS VGA (640 x 480) CAMERACHIPTM
Omni
ision
Table 5 provides a list and description of the Device Control registers contained in the OV7640/OV7141. For all register Enable/Disable bits, ENABLE=1 and DISABLE=0. The device slave addresses for the OV7640/OV7141 are 42 for write and 43 for read.
Table 5
Address (Hex) 00
SCCB Register List
Register Name GAIN Default (Hex) 00 R/W RW Description AGC - Gain control gain setting * Range: [00] to [FF] AWB - Blue channel gain setting
01
BLUE
80
RW
* Range: [00] to [FF] Note: This function is not available on the B&W OV7141. AWB - Red channel gain setting
02
RED
80
RW
* Range: [00] to [FF] Note: This function is not available on the B&W OV7141. Image Format - Color saturation value Bit[7:4]: Saturation value * Range: [0] to [F] Bit[3:0]: Reserved Note: This function is not available on the B&W OV7141. Image Format - Color hue control Bit[7:6]: Reserved Bit[5]: Hue Enable Bit[4:0]: Hue setting Note: This function is not available on the B&W OV7141. AWB - Red/Blue Pre-Amplifier gain setting Bit[7:4]: Red channel pre-amplifier gain setting * Range: [0] to [F] Bit[3:0]: Blue channel pre-amplifier gain setting * Range: [0] to [F] Note: This function is not available on the B&W OV7141.
03
SAT
84
RW
04
HUE
34
RW
05
CWF
3E
RW
06 07-09 0A 0B 0C-0F 10
BRT RSVD PID VER RSVD AECH
80 XX 76 48 XX 41
RW - R R - RW
ABC - Brightness setting * Range: [00] to [FF] Reserved Product ID number (Read only) Product version number (Read only) Reserved Exposure Value
10
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ision
Register Set
Table 5
Address (Hex)
SCCB Register List
Register Name Default (Hex) R/W Description Data Format and Internal Clock Bit[7:6]: Data Format - HSYNC/VSYNC Polarity 00: HSYNC = NEG VSYNC = POS 01: HSYNC = NEG VSYNC = NEG 10: HSYNC = POS VSYNC = POS 11: HSYNC = POS VSYNC = POS
11
CLKRC
00
RW
POS
NEG
Bit[5:0]:
Internal Clock Pre-Scalar * Range: [0 0000] to [F FFFF]
12
COMA
14
RW
Common Control A Bit[7]: SCCB - Register Reset 0: No change 1: Reset all registers to default values Bit[6]: Output Format - Mirror Image Enable Bit[5]: Reserved Bit[4]: Data Format - YUV formatting 0: Y U Y V Y U Y V 1: U Y V Y U Y V Y (default) Bit[3]: Output Format - Output Channel Select A 0: YUV/YCbCr 1: RGB/Raw RGB Bit[2]: AWB - Enable Bit[1:0]: Reserved Note: This function is not available on the B&W OV7141. Common Control B Bit[7:5]: Reserved Bit[4]: Data Format - ITU-656 Format Enable Bit[3]: Reserved Bit[2]: SCCB - Tri-State Enable - Y[7:0] Bit[1]: AGC - Enable Bit[0]: AEC - Enable
13
COMB
A3
RW
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OV7640/OV7141
Table 5
Address (Hex)
CMOS VGA (640 x 480) CAMERACHIPTM
Omni
ision
SCCB Register List
Register Name Default (Hex) R/W Description Common Control C Bit[7:6]: Reserved Bit[5]: Output Format - Resolution 0: VGA (640x480) 1: QVGA (320x240) Bit[4]: Reserved Bit[3]: Data Format - HREF Polarity 0: HREF Positive 1: HREF Negative
14
COMC
04
RW
POS
NEG
Bit[2:0]:
Reserved
15
COMD
00
RW
Common Control D Bit[7]: Data Format - Output Flag Bit Disable 0: Frame = 254 data bits (00/FF = Reserved flag bits) 1: Frame = 256 data bits Bit[6]: Data Format - Y[7:0]-PCLK Reference Edge 0: Y[7:0] data out on PCLK falling edge 1: Y[7:0] data out on PCLK rising edge Bit[5:1]: Reserved Bit[0]: Data Format - UV Sequence Exchange 0: V Y U Y V Y U Y 1: U Y V Y U Y V Y Note: Bit[0] is not programmable on the B&W OV7141. Reserved Output Format - Horizontal Frame (HREF Column) Start Output Format - Horizontal Frame (HREF Column) Stop Output Format - Vertical Frame (Row) Start Output Format - Vertical Frame (Row) Stop Data Format - Pixel Delay Select (Delays timing of the Y[7:0] data relative to HREF in pixel units) * Range: [00] (No delay) to [FF] (256 pixel delay)
16 17 18 19 1A 1B 1C 1D 1E
RSVD HSTART HSTOP VSTRT VSTOP PSHFT MIDH MIDL RSVD
XX 1A BA 03 F3 00 7F A2 XX
- RW RW RW RW RW R R -
Manufacturer ID Byte - High Manufacturer ID Byte - Low Reserved
(Read only = 0x7F) (Read only = 0xA2)
12
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ision
Register Set
Table 5
Address (Hex)
SCCB Register List
Register Name Default (Hex) R/W Description Output Format - Format Control Bit[7:5]: Reserved Bit[4]: Output Format - RGB:565 Enable Note: Bit[4] is not programmable on the B&W OV7141. Bit[3]: Reserved Bit[2]: Output Format - RGB:555 Enable Note: Bit[2] is not programmable on the B&W OV7141. Bit[1:0]: Reserved
1F
FACT
01
RW
20
COME
C0
RW
Common Control E Bit[7]: Reserved Bit[6]: AEC - Digital Averaging Enable Bit[5]: Reserved Bit[4]: Image Quality - Edge Enhancement Enable Bit[3:1]: Reserved Bit[0]: Y[7:0] 2X IOL / IOH Enable Reserved AGC/AEC - Stable Operating Region - Upper Limit AGC/AEC - Stable Operating Region - Lower Limit Common Control F Bit[7:3]: Reserved Bit[2]: Data Format - Output Data MSB/LSB Swap Enable (LSB MSB (Y[7]) and MSB LSB (Y[0]) Bit[1:0]: Reserved
21-23 24 25
RSVD AEW AEB
XX 10 8A
- RW RW
26
COMF
A2
RW
27
COMG
E2
RW
Common Control G Bit[7:5]: Reserved Bit[4]: Color Matrix - RGB Crosstalk Compensation Enable (Used to increase each color filter's efficiency) Note: Bit[4] is not programmable on the B&W OV7141. Bit[3:2]: Bit[1]: Reserved Data Format - Output Full Range Enable 0: Output Range = [10] to [F0] (224 bits) 1: Output Range = [01] to [FE] (254/256 bits) Reserved
Bit[0]:
28
COMH
20
RW
Common Control H Bit[7]: Output Format - RGB Output Select 0: RGB 1: Raw RGB Bit[6]: Device Select 0: OV7640 1: OV7141 Bit[5]: Output Format - Scan Select 0: Interlaced 1: Progressive Bit[4:0]: Reserved
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OV7640/OV7141
Table 5
Address (Hex) 29
CMOS VGA (640 x 480) CAMERACHIPTM
Omni
ision
SCCB Register List
Register Name COMI Default (Hex) 00 R/W R Description Common Control I Bit[7:2]: Reserved Bit[1:0]: Device Version (Read-only) Output Format - Frame Rate Adjust High Bit[7]: Data Format - Frame Rate Adjust Enable Bit[6:5]: Data Format - Frame Rate Adjust Setting MSB FRA[9:0] = MSB + LSB = FRARH[6:5] + FRARL[7:0] Bit[4]: A/D - UV Channel `2 Pixel Delay' Enable Note: Bit[4] is not programmable on the B&W OV7141. Bit[3:0]: Reserved
2A
FRARH
00
RW
2B 2C
FRARL RSVD
00 XX
RW -
Data Format - Frame Rate Adjust Setting LSB FRA[9:0] = MSB + LSB = FRARH[6:5] + FRARL[7:0] Reserved Common Control J Bit[7:3]: Reserved Bit[2]: AEC - Band Filter Enable Bit[1:0]: Reserved Reserved Signal Process Control B Bit[7]: AGC - 1.5x Multiplier (Pre-amplifier) Enable Bit[6:0]: Reserved Reserved Color Matrix - RGB Crosstalk Compensation - R Channel
2D
COMJ
81
RW
2E-5F 60 61-6B 6C
RSVD SPCB RSVD RMCO
XX 06 XX 11
- RW - RW
Note: This function is not available on the B&W OV7141. Color Matrix - RGB Crosstalk Compensation - G Channel 6D GMCO 01 RW Note: This function is not available on the B&W OV7141. Color Matrix - RGB Crosstalk Compensation- B Channel 6E 6F-70 BMCO RSVD 06 XX RW Note: This function is not available on the B&W OV7141. - Reserved Common Mode Control L Bit[7]: Reserved Bit[6]: Data Format - PCLK output gated by HREF Enable Bit[5]: Data Format - Output HSYNC on HREF Pin Enable Bit[4]: Reserved Bit[3:2]: Data Format - HSYNC Rising Edge Delay MSB Bit[1:0]: Data Format - HSYNC Falling Edge Delay MSB Data Format - HSYNC Rising Edge Delay LSB 72 HSDYR 10 RW HSYNCR[9:0] = MSB + LSB = COML[3:2] + HSDYR[7:0] * Range 000 to 762 pixel delays
71
COML
00
RW
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ision
Register Set
Table 5
Address (Hex)
SCCB Register List
Register Name Default (Hex) R/W Description Data Format - HSYNC Falling Edge Delay LSB
73
HSDYF
50
RW
HSYNCF[9:0] = MSB + LSB = COML[1:0] + HSDYF[7:0] * Range 000 to 762 pixel delays Common Mode Control M Bit[7]: Reserved Bit[6:5]: AGC - Maximum Gain Select 00: +6 dB 01: +12 dB 10: +6 dB 11: +18 dB Bit[4:0]: Reserved Common Mode Control N Bit[7]: Output Format - Vertical Flip Enable Bit[6:0]: Reserved Common Mode Control O Bit[7:6]: Reserved Bit[5]: Standby Mode Enable Bit[4:3]: Reserved Bit[2]: SCCB - Tri-State Enable - VSYNC, HREF and PCLK Bit[1:0]: Reserved Reserved AEC - Digital Y/G Channel Average (Automatically updated by AGC/AEC, user can only read the values) AEC - Digital R/V Channel Average (Automatically updated by AGC/AEC, user can only read the values) Note: This function is not available on the B&W OV7141. AEC - Digital B/U Channel Average (Automatically updated by AGC/AEC, user can only read the values) Note: This function is not available on the B&W OV7141.
74
COMM
20
RW
75
COMN
02
RW
76
COMO
00
RW
77-7D 7E
RSVD AVGY
XX 00
- RW
7F
AVGR
00
RW
80
AVGB
00
RW
NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings.
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OV7640/OV7141
CMOS VGA (640 x 480) CAMERACHIPTM
Omni
ision
Package Specifications
The OV7640/OV7141 uses a 28-pin plastic package. Refer to Figure 10 for package information, Table 6 for package dimensions, and Figure 11 for the array center on the chip.
Figure 10 OV7640OV7141 Plastic Package Specifications
.093 .004 .042 .002 .300 .004 .050 .004 .050 TYP 4 5 .012 x 45 o 11 12 .022 .002 .001 to .005 TYP 12 9 .075 .004 .028 .002 11 8 7 6 .450 SQ .004 .350 SQ .006 .275 SQ .004 5 4
Pin 1 Index 1
.406 .004
.010 x 45 o Chamfer Pin 1 Index
1 28
1
28
28
20 26 25 19 18 18 21 19 .035 MIN. .085 TYP .025 .003 TYP .009 R REF TYP 22 25
23 26
.028 .002 (Metallized)
Table 6
OV7640/OV7141 Plastic Package Dimensions
Dimensions Millimeters (mm) 11.43 + 0.10 SQ 2.35 + 0.1 0.70 + 0.05 7.00 + 0.10 SQ 1.07 + 0.05 0.64 x 2.16 0.64 x 1.27 1.27 + 0.10 1.90 + 0.10 7.62 + 0.10 10.30 + 0.10 SQ 0.55 + 0.05 Inches (in.) .450 + .004 SQ .093 + .004 .028 + .002 .275 + .004 SQ .042 + .002 .025 x .085 .025 x .050 .050 + .004 .075 + .004 .300 + .004 .406 + .004 SQ .022 + .002 Version 1.4, March 6, 2003
Package Size Package Height Substrate Height Cavity Size Castellation Height Pin #1 Pad Size Pad Size Pad Pitch Package Edge to First Lead Center End-to-End Pad Center-Center Glass Size Glass Height 16 Proprietary to OmniVision Technologies
Omni
ision
Package Specifications
Sensor Array Center
Figure 11 OV7640/OV7141 Sensor Array Center
Pin 1
3.6512 mm
Array Center (0.2273, 0.1222)
2.7328 mm
Die Y-Centerline
Image Array
OV7640/OV7141 Die
Die X-Centerline
Positional Tolerances Die shift (x,y) = 0.15 mm (6 mils) max. Die tilt = 1 degrees max. Die rotation = 3 degrees max.
NOTES: Due to the lens inversion, in order for the image to be right-side up, the OV7640/OV7140 must be mounted Pin 1 down. Picture is for reference only, not to scale.
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OV7640/OV7141
CMOS VGA (640 x 480) CAMERACHIPTM
Omni
ision
IR Reflow Ramp Rate Requirements
Figure 12 IR Reflow Ramp Rate Requirements
Typical Dwell Time = 10Sec
230oC 220oC 210oC 200oC 190oC 180oC 170oC 160oC 150oC 140oC 130oC
Ramp Rate: 10o/minute
o Maximum Dwell Time > 215 = 30Sec
Ramp Rate: 50o/minute
25 oC
60S Note:
120S
180S
240S
All temperatures = 10 oC All times show the fastest allowable ramp rate
18
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ision
Package Specifications
Note:
* All information shown herein is current as of the revision and publication date. Please refer to the OmniVision web site (http://www.ovt.com) to obtain the current versions of all documentation. OmniVision Technologies, Inc. reserves the right to make changes to their products or to discontinue any product or service without further notice (It is advisable to obtain current product documentation prior to placing orders). Reproduction of information in OmniVision product documentation and specifications is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. In such cases, OmniVision is not responsible or liable for any information reproduced. This document is provided with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification or sample. Furthermore, OmniVision Technologies Inc. disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this document. No license, expressed or implied, by estoppels or otherwise, to any intellectual property rights is granted herein. `OmniVision', `CameraChip' are trademarks of OmniVision Technologies, Inc. All other trade, product or service names referenced in this release may be trademarks or registered trademarks of their respective holders. Third-party brands, names, and trademarks are the property of their respective owners.
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For further information, please feel free to contact OmniVision at info@ovt.com.
OmniVision Technologies, Inc. Sunnyvale, CA USA (408) 733-3030
Version 1.4, March 6, 2003
Proprietary to OmniVision Technologies
19
OV7640/OV7141
CMOS VGA (640 x 480) CAMERACHIPTM
Omni
ision
20
Proprietary to OmniVision Technologies
Version 1.4, March 6, 2003

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